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LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTIO
The LTC(R)2605/LTC2615/LTC2625 are octal 16-, 14and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use the 2-wire I2C compatible serial interface. The LTC2605/LTC2615/LTC2625 operate in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum clock rate of 400kHz). The LTC2605/LTC2615/LTC2625 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2605-1/ LTC2615-1/LTC2625-1 to midscale. The voltage output stays at midscale until a valid write and update takes place.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES

Smallest Pin-Compatible Octal DACs: LTC2605: 16 Bits LTC2615: 14 Bits LTC2625: 12 Bits Guaranteed Monotonic Over Temperature 400kHz I2C Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk Between DACs (<10V) High Rail-to-Rail Output Drive (15mA, Min) Double-Buffered Digital Inputs 27 Selectable Addresses LTC2605/LTC2615/LTC2625: Power-On Reset to Zero Scale LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset to Midscale Tiny 16-Lead Narrow SSOP Package
APPLICATIO S

Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
GND 1 VOUT A 2 DAC A
16 VCC
REGISTER
REGISTER
REGISTER
REGISTER
DAC H
15 VOUT H
REGISTER
REGISTER
REGISTER
REGISTER
VOUT B
3
DAC B
DAC G
14 VOUT G
REGISTER
REGISTER
REGISTER
REGISTER
DNL (LSB)
VOUT C
4
DAC C
DAC F
13 VOUT F
REGISTER
REGISTER
REGISTER
REGISTER
VOUT D
5
DAC D
DAC E
12 VOUT E
REF
6 32-BIT SHIFT REGISTER
11
CA0
CA2
7
10
CA1
2-WIRE INTERFACE SCL 8
9
2605/15/25 BD
SDA
U
W
U
Differential Nonlinearity (LTC2605)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2605 G02
VCC = 5V VREF = 4.096V
2605f
1
LTC2605/LTC2615/LTC2625 ABSOLUTE AXI U RATI GS
Any Pin to GND ........................................... - 0.3V to 6V Any Pin to VCC .............................................- 6V to 0.3V Maximum Junction Temperature .......................... 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CA2 SCL 1 2 3 4 5 6 7 8 16 VCC 15 VOUT H 14 VOUT G 13 VOUT F 12 VOUT E 11 CA0 10 CA1 9 SDA
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 150C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Resolution Monotonicity DNL INL Integral Nonlinearity Load Regulation (Note 2) (Note 2) VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.7V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking ZSE VOS Zero-Scale Error Offset Error VOS Temperature Coefficient GE Gain Error Gain Temperature Coefficient
ELECTRICAL CHARACTERISTICS
CONDITIONS
DC Performance

Differential Nonlinearity (Note 2)
Code = 0 (Note 4)
2
U
U
W
WW
U
W
(Note 1)
Operating Temperature Range LTC2605C/LTC2615C/LTC2625C ............. 0C to 70C LTC2605C-1/LTC2615C-1/LTC2625C-1 ... 0C to 70C LTC2605I/LTC2615I/LTC2625I ............ - 40C to 85C LTC2605I-1/LTC2615I-1/LTC2625I-1 .. - 40C to 85C
ORDER PART NUMBER LTC2605CGN LTC2605CGN-1 LTC2605IGN LTC2605IGN-1 LTC2615CGN LTC2615CGN-1 LTC2615IGN LTC2615IGN-1 LTC2625CGN LTC2625CGN-1 LTC2625IGN LTC2625IGN-1
GN PART MARKING 2605 26051 2605I 26O5I1 2615 26151 2615I 2615I1 2625 26251 2625I 2625I1
LTC2625/-1 MIN TYP MAX 12 12 0.5 1 4
LTC2615/-1 MIN TYP MAX 14 14 1 4 0.07 0.10 0.15 0.20 1.7 1 5 16 0.5 0.5 1 1 9 9
LTC2605/-1 MIN TYP MAX 16 16 1 18 0.3 0.4 0.6 0.8 1.7 1 5 64 2 2 4 4 9 9
UNITS Bits Bits LSB LSB LSB/mA LSB/mA LSB/mA LSB/mA mV mV V/C
0.02 0.125 0.03 0.125 0.04 0.07 1.7 1 5 0.1 8 0.7 0.25 0.25 9 9
0.1 8
0.7
0.1 8
0.7
%FSR ppm/C
2605f
LTC2605/LTC2615/LTC2625
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. (Note 9)
SYMBOL PSR ROUT PARAMETER Power Supply Rejection DC Output Impedance DC Crosstalk (Note 10) CONDITIONS VCC 10% VREF = VCC = 5V, Midscale; -15mA IOUT 15mA VREF = VCC = 2.7V, Midscale; -7.5mA IOUT 7.5mA Due to Full Scale Output Change (Note 11) Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.7V, VREF = 2.7V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current, Power Down Mode DAC Powered Down Positive Supply Voltage Supply Current For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) DAC Powered Down (Note 3) VCC = 5V DAC Powered Down (Note 3) VCC = 3V

ELECTRICAL CHARACTERISTICS
MIN
TYP -80 0.02 0.03 10 3.5 7
MAX 0.15 0.15
UNITS dB V V/mA V
ISC
Short-Circuit Output Current
15 15 7.5 7.5 0 11
34 34 20 27
60 60 50 50 VCC
mA mA mA mA V k pF A V mA mA A A V V
Normal Mode
16 90 0.001
20 1 5.5
Power Supply 2.7 2.50 2.00 0.38 0.16 4.0 3.2 1.0 1.0 0.3VCC 0.7VCC 0.15VCC 0.85VCC 10 10 2 0 0.4 250 50 1 10 400 10
Digital I/O (Note 9) VIL VIH VIL(CA) VIH(CA) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAn Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage (CA0 to CA2) High Level Input Voltage (CA0 to CA2) Resistance from CAn (n = 0,1,2) to VCC to Set CAn = VCC Resistance from CAn (n = 0,1,2) to GND to Set CAn = GND Resistance from CAn (n = 0,1,2) to VCC or GND to Set CAn = FLOAT Low Level Output Voltage Output Fall Time Pulse Width of Spikes Surpassed by Input Filter Input Leakage I/O Pin Capacitance Capacitance Load for Each Bus Line External Capacitive Load on Address Pins CA0, CA1 and CA2 0.1VCC VIN 0.9VCC (Note 12) See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 7)

V V k k M V ns ns A pF pF pF
20 + 0.1CB
0
2605f
3
LTC2605/LTC2615/LTC2625
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER AC Performance tS Settling Time (Note 5) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 7 7 9 2.7 4.8 0.80 1000 12 180 120 100 15 7 9 10 2.7 4.8 5.2 0.80 1000 12 180 120 100 15 s s s s s s V/s pF nV * s kHz nV/Hz nV/Hz VP-P CONDITIONS LTC2625/-1 MIN TYP MAX LTC2615/-1 MIN TYP MAX LTC2605/-1 MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Settling Time for 1LSB Step (Note 6) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise
2.7
0.80 1000 At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 12 180 120 100 15
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Notes 8, 9)
SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Clock Pin High Period of the SCL Clock Pin Set-Up Time for a Repeated Start Program Data Hold Time Data Set-Up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Stop and Start Condition (Note 7) (Note 7) CONDITIONS

TI I G CHARACTERISTICS
VCC = 2.7V to 5.5V 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 300 300 0.9 400 kHz s s s s s ns ns ns s s
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating. Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1), code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and at full scale. Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
4
UW
MIN
TYP
MAX
UNITS
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale and half scale - 1. Load is 2k in parallel with 200pF to GND. Note 7: CB = capacitance of one bus line in pF. Note 8: All values refer to VIH(MIN) and VIL(MAX) levels. Note 9: These specifications apply to LTC2605/LTC2605-1, LTC2615/ LTC2615-1 and LTC2625/LTC2625-1. Note 10: DC Crosstalk is measured with VCC = 5V and VREF = 4096V, with the measured DAC at midscale, unless otherwise noted. Note 11: RL = 2k to GND or VCC. Note 12: Guaranteed by design and not production tested.
2605f
LTC2605/LTC2615/LTC2625
ELECTRICAL CHARACTERISTICS
Test Circuit 1
100 CAn
RINH/RINL/RINF
Test Circuit 2
VDD
VIH(CAn)/VIL(CAn)
2605/15/25 EC01
2605/15/25 EC02
GND
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605
Integal Nonlinearity (INL)
32 24 16 DNL (LSB) INL (LSB) 8 0 -8 -16 -24 -32 0 16384 32768 CODE 49152 65535
2605 G01
VCC = 5V VREF = 4.096V
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2605 G02
INL (LSB)
DNL vs Temperature
1.0 0.8 0.6 16 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -16 -0.6 -0.8 -1.0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -24 -32 DNL (NEG) DNL (POS) INL (LSB) 8 0 -8 VCC = 5V VREF = 4.096V 32 24
DNL (LSB)
UW
2605 G04
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 16 8 0 -8 -16 -24 VCC = 5V VREF = 4.096V 32 24
INL vs Temperature
VCC = 5V VREF = 4.096V
INL (POS)
INL (NEG)
-32 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2605 G03
INL vs VREF
VCC = 5.5V 1.5 1.0 INL (POS) 0.5
DNL vs VREF
VCC = 5.5V
DNL (POS) 0 DNL (NEG) -0.5 -1.0 -1.5
INL (NEG)
0
1
2 3 VREF (V)
4
5
2605 G05
0
1
2 3 VREF (V)
4
5
2605 G06
2605f
5
LTC2605/LTC2615/LTC2625 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605
Settling to 1LSB Settling of Full-Scale Step
VOUT 100V/DIV 9TH CLOCK OF 3RD DATA BYTE 9.7s
SCL 2V/DIV
VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
LTC2615
Integral Nonlinearity (INL)
8 6 4 DNL (LSB) INL (LSB) 2 0 -2 -4 -6 -8 0 4096 8192 CODE 12288 16383
2605 G09
VCC = 5V VREF = 4.096V
LTC2625
Integral Nonlinearity (INL)
2.0 1.5 1.0
DNL (LSB)
VCC = 5V VREF = 4.096V
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 0 1024 2048 CODE 3072 4095
2605 G12
6
UW
VOUT 100V/DIV
12.3s 9TH CLOCK OF 3RD DATA BYTE
SCR 2V/DIV
2605 G07
2s/DIV
5s/DIV SETTLING TO 1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS
2605 G08
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16383
2605 G10
Settling to 1LSB
VCC = 5V VREF = 4.096V
VOUT 100V/DIV 9TH CLOCK OF 3RD DATA BYTE 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
SCL 2V/DIV
8.9s
2605 G11
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2605 G13
Settling to 1LSB
VCC = 5V VREF = 4.096V
6.8s VOUT 1mV/DIV 9TH CLOCK OF 3RD DATA BYTE 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS
2605 G14
SCL 2V/DIV
2605f
LTC2605/LTC2615/LTC2625 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605/LTC2615/LTC2625
Current Limiting
0.10 0.08 0.06 0.04 1.0 CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V 0.8 0.6 OFFSET ERROR (mV) 25 35 0.4 2 1 0 -1 -2 -3 -50
VOUT (mV)
VOUT (V)
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -40 -30 -20 -10 0 10 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V
Zero-Scale Error vs Temperature
3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 -50 0.4 0.3
OFFSET ERROR (mV)
-30
-10 10 30 50 TEMPERATURE (C)
Gain Error vs VCC
0.4 0.3 0.2
GAIN ERROR (%FSR)
0.1
ICC (nA)
0 -0.1 -0.2
-0.3 -0.4 2.5
3
3.5
4 VCC (V)
4.5
UW
70
2605 G18
Load Regulation
CODE = MIDSCALE 3
Offset Error vs Temperature
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 VREF = VCC = 3V VREF = VCC = 5V
-30
-10 10 30 50 TEMPERATURE (C)
70
90
2605 G15
2606 G16
2605 G17
Gain Error vs Temperature
3 2 1 0 -1 -2
Offset Error vs VCC
0.2 0.1 0 -0.1 -0.2 -0.3
90
-0.4 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
-3 2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2605 G20
2605 G19
ICC Shutdown vs VCC
450 400 350 300 250 200 150 100 50
5 5.5
2605 G21
Large-Signal Response
VOUT 0.5V/DIV
VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5s/DIV
2605 G23
0 2.5
3
3.5
4 VCC (V)
4.5
5
5.5
2605 G22
2605f
7
LTC2605/LTC2615/LTC2625 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605/LTC2615/LTC2625
Midscale Glitch Impulse Power-On Reset Glitch
5.0 4.5 5V SOURCING
TRANSITION FROM MS-1 TO MS VOUT 10mV/DIV 9TH CLOCK OF 3RD DATA BYTE TRANSITION FROM MS TO MS-1 4mV PEAK VOUT 10mV/DIV
2605 G24
VOUT (V)
SCL 2V/DIV
2.5s/DIV
Power-On Reset to Midscale
VREF = VCC
ICC (mA)
1V/DIV
2.3 2.2 2.1
dB
VCC VOUT 500s/DIV
2605 G27
Output Voltage Noise, 0.1Hz to 10Hz
40mA 30mA 20mA
10mA/DIV
0mA
10mA/DIV
VOUT 10V/DIV
0
1
2
3
456 SECONDS
7
8
UW
8 9
Headroom at Rails vs Output Current
4.0
VCC 1V/DIV
3.5 3.0 2.5 2.0 1.5 1.0 5V SINKING 3V SINKING 3V SOURCING
250s/DIV
2605 G25
0.5 0 0 1 2 3
456 IOUT (mA)
7
8
9
10
2605 G26
Supply Current vs Logic Voltage
2.8 2.7 2.6 2.5 2.4 VCC = 5V SWEEP SCL AND SDA 0V TO VCC AND VCC TO 0V
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36
Multiplying Bandwidth
2.0 0 1 3 2 LOGIC VOLTAGE (V) 4 5
2605 G28
VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 1k 10k 100k FREQUENCY (Hz) 1M
2605 G29
Short-Circuit Output Current vs VOUT (Sinking)
0mA -10mA -20mA -30mA -40mA -50mA
Short-Circuit Output Current vs VOUT (Sourcing)
10mA
10
VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 0 1 2 3 4 5 1V/DIV
VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 01 1V/DIV 2 3 4 5
2605 G32
2605 G30
2605 G31
2605f
LTC2605/LTC2615/LTC2625
PIN FUNCTIONS
GND (Pin 1): Analog Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Output. The output range is 0V to VREF. REF (Pin 6): Reference Voltage Input. 0V VREF VCC. CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This is a high impedance pin while data is shifted in. It is an opendrain N-channel output during acknowledgment. This pin requires a pull-up resistor or current source to VCC. CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). VCC (Pin 16): Supply Voltage Input. 2.7V VCC 5.5V.
BLOCK DIAGRA
GND VOUT A
1
DAC REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER
2
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
VOUT B
3
DAC B
DAC REGISTER
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
VOUT C
DAC REGISTER
4
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
VOUT D
5
DAC D
DAC REGISTER
REF
6 32-BIT SHIFT REGISTER
CA2
7
SCL
8
TI I G DIAGRA
SDA tf SCL
tLOW
S
tHD(STA)
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
W
W
U
U
UW
U
16 VCC
DAC A
DAC H
15 VOUT H
DAC G
14 VOUT G
DAC C
DAC F
13 VOUT F
DAC E
12 VOUT E
11
CA0
10
CA1
2-WIRE INTERFACE
9
2605/15/25 BD01
SDA
tr
tSU(DAT)
tf
tHD(STA)
tSP
tr
tBUF
tHD(DAT)
tHIGH
tSU(STA)
S
tSU(STO)
P
S
2605/15/25 TD01
Figure 1
2605f
9
LTC2605/LTC2615/LTC2625
OPERATIO
Power-On Reset
The LTC2605/LTC2615/LTC2625 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. The LTC2605-1/ LTC2615-1/LTC2625-1 set the voltage outputs to midscale when power is first applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2605/ LTC2615/LTC2625 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range - 0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = N VREF 2
Table 1.
COMMAND* C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1
*Address and command codes not shown are reserved and should not be used.
10
U
where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Digital Interface The LTC2605/LTC2615/LTC2625 communicate with a host using the standard 2-wire digital interface. The Timing Diagram (Figure 1) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2605/LTC2615/LTC2625 are receive-only (slave) devices. The master can write to the LTC2605/LTC2615/ LTC2625. The LTC2605/LTC2615/LTC2625 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device.
ADDRESS (n)* A3 A2 A1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 A0 0 1 0 1 0 1 0 1 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs
2605f
LTC2605/LTC2615/LTC2625
OPERATIO
S
WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625 SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE INPUT WORD INPUT WORD (LTC2605) C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 2ND DATA BYTE A1 A0 D13 D12 D11 D10 D9 D8 D7 D8 D7 D6 D5 D4 D3 D2 D1 D0 A 3RD DATA BYTE A P
INPUT WORD (LTC2615) C3 C2 C1 C0 A3 A2 D6 D5 D4 D3 D2 D1 D0 X X
INPUT WORD (LTC2625) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
2605/2615/2625 O01
Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2605/LTC2615/LTC2625 respond to a write by a master in this manner. The LTC2605/LTC2615/LTC2625 do not acknowledge a read (it retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC, GND or FLOAT. This results in 27 selectable addresses for the part. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 2. In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2605, LTC2615 and LTC2625 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit hardwired address and is not selectable by CA0, CA1 and CA2. The
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1ST DATA BYTE 3RD DATA BYTE 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
Figure 2
maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF. Write Word Protocol The master initiates communication with the LTC2605/ LTC2615/LTC2625 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2605/LTC2615/LTC2625 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of data. The LTC2605/LTC2615/LTC2625 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2605/ LTC2615/LTC2625 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2605/LTC2615/LTC2625 do not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 2. The first byte of the input word consists of the 4-bit command and 4bit DAC address. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, followed by 0, 2 or 4 don't care bits (LTC2605, LTC2615 and LTC2625 respectively). A typical I2C write transaction is shown in Figure 3.
2605f
11
LTC2605/LTC2615/LTC2625
OPERATIO
The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads the 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the block diagram.
Table 2. Slave Address Map
CA2 CA1 CA0 SA6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SA4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GND GND GND GND GND FLOAT GND GND VCC GND FLOAT GND GND FLOAT FLOAT GND FLOAT VCC GND VCC GND GND VCC FLOAT GND VCC VCC FLOAT GND GND FLOAT GND FLOAT FLOAT GND VCC FLOAT FLOAT GND FLOAT FLOAT FLOAT FLOAT FLOAT VCC FLOAT VCC GND FLOAT VCC FLOAT FLOAT VCC VCC VCC GND GND VCC GND FLOAT VCC GND VCC VCC FLOAT GND VCC FLOAT FLOAT VCC FLOAT VCC VCC VCC GND VCC VCC FLOAT VCC VCC VCC GLOBAL ADDRESS
12
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Power Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers and reference inputs are disabled and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 90k resistors. When all eight DACs are powered down, the bias generation circuit is also disabled. Input- and DAC- registers are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100 b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 1/8 for each DAC powered down; the effective resistance at REF (Pin 6) rises accordingly, becoming a high-impedance input (typically >1G) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the updated command, the power-up delay is 5s. If, on the other hand, all eight DACs are powered down, then the bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12s for VCC = 5V, 30s for VCC = 3V. Voltage Outputs Each of the eight rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA.
2605f
LTC2605/LTC2615/LTC2625
OPERATIO
DC output impedance is equivalent to load regulation and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifier's DC output impedance is 0.020 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30 * 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance to just 0.005. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other.
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Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.020), and will degrade DC crosstalk. Note that the LTC2605/LTC2615/LTC2625 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
2605f
13
LTC2605/LTC2615/LTC2625
SLAVE ADDRESS COMMAND MS DATA A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 SA0 WR C3 C2 C1 C0 A3
LS DATA D5 D4 D3 D2 D1 D0 STOP
SA6
SA5
SA4
SA3
SA2
SA1
START SA0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ACK ACK ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK
SDA
SA6
SA5
SA4
SA3
SA2
SA1
SCL
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE
VOUT
Figure 3. Typical LTC2605 Input Waveform--Programming DAC Output for Full Scale
2605/15/25 O02
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OPERATIO
14
2605f
LTC2605/LTC2615/LTC2625
OPERATIO U
VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535 INPUT CODE (b)
2605/15/25 O05
0V NEGATIVE OFFSET
Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0250 TYP
1 .015 .004 x 45 (0.38 0.10) 0 - 8 TYP
.053 - .068 (1.351 - 1.727)
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.008 - .012 (0.203 - 0.305)
.0250 (0.635) BSC
GN16 (SSOP) 0502
2605f
15
LTC2605/LTC2615/LTC2625
TYPICAL APPLICATIO
ADDRESS SELECTION VCC VCC VCC
Demonstration Circuit--LTC2428 20-Bit ADC Measures Key Performance Parameters
VREF C1 0.1F C2 0.1F VCC VOUT A VOUT B VOUT C VOUT D VOUT E 10k I2C BUS 10k 9 8 SDA SCL GND 1 U2 LTC2605CGN VOUT F VOUT G VOUT H 16 2 3 4 5 12 13 14 15 TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D DAC OUTPUTS TP7 DAC E TP8 DAC F TP9 DAC G TP10 DAC H VIN 2 U4 LT1236ACS8-5 VIN GND C6 0.1F 4 VOUT 6 1 5V 4.096V 2 3 JP2 VREF C7 4.7F 6.3V TP11 VREF VREF 9 10 11 12 13 14 6 1 5VREF C8 REGULATOR 1F 16V 2 3 JP3 VCC 5V TP12 VCC TP13 GND 5 ZSSET FO GND GND GND GND GND GND GND 6 16 18 22 27 28 VCC 15 17 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 26 R7 7.5k
2605 TA01
VCC
U5 LT1461ACS8-4 2 3 C9 0.1F VIN SHDN GND 4 VOUT
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2606/LTC2616/ LTC2626 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10-/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs with I2C Interface in 10-Lead DFN COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5s/750A, 8s/450A VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2s for 10V Step 250A per DAC, 2.5V-5.5V Supply Range, Rail-to-Rail Output, SPI Interface 300A per DAC, 2.5V-5.5V Supply Range, Rail-to-Rail Output, SPI Interface 300A per DAC, 2.5V-5.5V Supply Range, Rail-to-Rail Output, SPI Interface 250A per DAC, 2.5V-5.5V Supply Range, Rail-to-Rail Output, SPI Interface 270A per DAC, 2.7V-5.5V Supply Range, Rail-to-Rail Output, I2C Interface
2605f LT/LWI/TP 0405 500 * PRINTED IN THE USA
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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VCC 6 REF 11 10 7 CA0 CA1 CA2 VREF VCC VCC R5 7.5k C10 100pF 7 MUXOUT 4 ADCIN 3 FSSET R8 22 2 8 C4 0.1F C5 0.1F JP1 ON/OFF DISABLE ADC 3 2 1 VCC VCC CSADC CSMUX 4-/8-CHANNEL MUX SCK CLK DIN SD0 23 20 25 19 21 24 SCK SPI BUS R6 7.5k CS
+
20-BIT ADC
-
1 U3 LTC2428CG
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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